Characterization of Stress in High Performance Server Microprocessors

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials, second level solder joints, organic PCB, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high CTE ceramic substrates, lead free solder joints, higher level of power generation, and larger heat sinks. Die stress effects are of concern due to the possible degradation of silicon device performance (mobility/speed) and due to the possible damage that can occur to the copper/low-k top level interconnect layers. In this work, we have used test chips containing piezoresistive sensors to measure the stresses induced in microprocessor die after various steps of the assembly process. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 x 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to the high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the stress test die. The chips were reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. The build-up of the die stresses was found to be monotonically increasing, and the relative severity of each assembly step was judged and compared. Such an approach allows for various material sets (solders, underfills, TIM materials, lid metals, and lid adhesives) to be analyzed and rated for their contribution to the die stress level. INTRODUCTION Microprocessor packaging in modern high performance workstations and servers often consists of one or more large flip chip die that are mounted to a high density ceramic chip carrier. Figure 1 illustrates a typical configuration with an air-cooled heat sink. Over the past few years, the flip chip solder interconnects have transitioned to full area arrays and lead free composition, while the size of the processor die has grown dramatically. In addition, the utilized Ceramic Ball Grid Array (CBGA) substrates are now typically constructed from “high CTE” glass ceramic materials [1-7]. Relative to the older alumina ceramic technology with tungsten based conductors, these new ceramics have significantly higher coefficients of thermal expansion (10-12 ppm/C) and much lower stiffness (70-80 GPa). They are also formed with much lower co-firing temperatures, which allows processing with higher performance copper-based conductors. Elements completing the basic processor package are the underfill between the chip and the chip carrier, and a metal lid (AlSiC) adhered to the top of the ceramic carrier with an adhesive and to the back of the die through a Proceedings of the XIth International Congress and Exposition June 2-5, 2008 Orlando, Florida USA ©2008 Society for Experimental Mechanics Inc. thermal interface material (TIM1). The processor package can be used as a Land Grid Array (LGA) in a socket, or as a Ceramic Ball Grid Array attached to a high density PCB if an additional set of second level solder interconnects are added to the bottom of the ceramic chip carrier. In either case, a heat sink is normally bonded (TIM2) and mechanically clamped to the metallic lid on the chip carrier.